Re: Improving spin-lock implementation on ARM. - Mailing list pgsql-hackers

Alexander Korotkov <aekorotkov@gmail.com> writes:
> On Thu, Nov 26, 2020 at 1:32 PM Heikki Linnakangas <hlinnaka@iki.fi> wrote:
>> Is there some official ARM documentation, like a programmer's reference
>> manual or something like that, that would show a reference
>> implementation of a spinlock on ARM? It would be good to refer to an
>> authoritative source on this.

> I've compared assembly output of gcc implementations of CAS and TAS.

FWIW, I see quite different assembly using Apple's clang on their M1
processor.  What I get for SpinLockAcquire on HEAD is (lock pointer
initially in x0):

    mov    x19, x0
    mov    w8, #1
    swpal    w8, w8, [x0]
    cbz    w8, LBB0_2
    adrp    x1, l_.str@PAGE
    add    x1, x1, l_.str@PAGEOFF
    adrp    x3, l___func__.foo@PAGE
    add    x3, x3, l___func__.foo@PAGEOFF
    mov    x0, x19
    mov    w2, #12
    bl    _s_lock
LBB0_2:
    ... lock is acquired

while SpinLockRelease is just

    stlr    wzr, [x19]

With the patch, I get

    mov    x19, x0
    mov    w8, #0
    mov    w9, #1
    casa    w8, w9, [x0]
    cmp    w8, #0                  ; =0
    b.eq    LBB0_2
    adrp    x1, l_.str@PAGE
    add    x1, x1, l_.str@PAGEOFF
    adrp    x3, l___func__.foo@PAGE
    add    x3, x3, l___func__.foo@PAGEOFF
    mov    x0, x19
    mov    w2, #12
    bl    _s_lock
LBB0_2:
    ... lock is acquired

and SpinLockRelease is the same.

Don't know much of anything about ARM assembly, so I don't
know if these instructions are late-model-only.

            regards, tom lane