Thread: Status of Opteron vs Xeon
What's the current status of how much faster the Opteron is compared to the Xeons? I know the Opterons used to be close to 2x faster, but is that still the case? I understand much work has been done to reduce the contect switching storms on the Xeon architecture, is this correct? -- Jeff Frost, Owner <jeff@frostconsultingllc.com> Frost Consulting, LLC http://www.frostconsultingllc.com/ Phone: 650-780-7908 FAX: 650-649-1954
> What's the current status of how much faster the Opteron is compared to > the > Xeons? I know the Opterons used to be close to 2x faster, but is that > still > the case? I understand much work has been done to reduce the contect > switching storms on the Xeon architecture, is this correct? Up until two days ago (Oct 5) Intel has had no answer for AMD's dual core offerings...unfortunately this has allowed AMD to charge top dollar for dual core Opterons. The Intel dual core solution on the P4 side hasn't been very impressive particularly with regard to thermals. My 90nm athlon 3000 at home runs very cool...if I underclock it a bit I can actually turn off the cooling fan :). IMO, right now it's AMD all the way, but if you are planning a big purchase, it might be smart to wait a couple of months for the big price realignment as Intel's dual xeons hit the retail channel. Merlin
jeff@frostconsultingllc.com (Jeff Frost) writes: > What's the current status of how much faster the Opteron is compared > to the Xeons? I know the Opterons used to be close to 2x faster, > but is that still the case? I understand much work has been done to > reduce the contect switching storms on the Xeon architecture, is > this correct? Work has gone into 8.1 to try to help with the context switch storms; that doesn't affect previous versions. Furthermore, it does not do anything to address the consideration that memory access on Opterons seem to be intrinsically faster than on Xeon due to differences in the memory bus architecture. The only evident ways to address that are: a) For Intel to deploy chips with better memory buses; b) For Intel to convince people to deploy compilers that optimize badly on AMD to make Intel chips look better... -- (format nil "~S@~S" "cbbrowne" "ntlug.org") http://cbbrowne.com/info/lsf.html A mathematician is a machine for converting caffeine into theorems.
Chris Browne <cbbrowne@acm.org> writes: > jeff@frostconsultingllc.com (Jeff Frost) writes: >> What's the current status of how much faster the Opteron is compared >> to the Xeons? I know the Opterons used to be close to 2x faster, >> but is that still the case? I understand much work has been done to >> reduce the contect switching storms on the Xeon architecture, is >> this correct? > Work has gone into 8.1 to try to help with the context switch storms; > that doesn't affect previous versions. Also note that we've found that the current coding of the TAS macro seems to be very bad for at least some Opterons --- they do much better if the "pre-test" cmpb is removed. But this is not true for all x86_64 chips. We still have an open issue about what to do about this. regards, tom lane
> > Furthermore, it does not do anything to address the consideration that > memory access on Opterons seem to be intrinsically faster than on Xeon > due to differences in the memory bus architecture. > I have been running some tests using different numa policies on a quad Opteron server and have found some significant performance differences depending on the type of load the system is under. It's not clear to me yet if I can draw any general conclusions from the results though. Emil