Possible Spinlock impact of highly increased latency of PAUSE instruction on Skylake - Mailing list pgsql-hackers

Hi all,

I just read an article about a recent architecture change in newer Intel processors.

As mentioned in

[1] https://aloiskraus.wordpress.com/2018/06/16/why-skylakex-cpus-are-sometimes-50-slower-how-intel-has-broken-existing-code/

Intel changed the latency respective reciproque throughput of the PAUSE instruction from about 9 clock cycles on Haswell to 141 cycles on Skylake class of processors.

This correlates to the findings of Agner Fog in its instruction tables, see

[2] http://www.agner.org/optimize/

and is also documented by Intel (see [1]).

This caused a massive regression in a .NET application from 9.1s to 19s.
For .NET core a patch was quickly introduced.

I am aware that PostgreSQl also uses the PAUSE instruction for Spinlocks (in arch-x86.h: pg_spin_delay_impl(void)).

I have no access to such newer hardware nor do I have experience in hacking and performance tests.

I want to bring this to notice to everyone to determine if there is an impact of this change for Postgres too.

Perhaps someone can check it out in the process of PG11 maturing.

Thanks

Hans Buschmann