Re: Detection of hadware feature => please do not use signal - Mailing list pgsql-bugs

Thomas Munro <thomas.munro@gmail.com> writes:
> The GCC docs give only +nofp, not +fp as an option for 32 bit armv8-a
> (that is, under "ARM options", as opposed to "aarch64 options").  But
> I guess GCC is pretty configurable and NetBSD targets some weird
> hardware... as for why it could be like that (if not a mistake), it
> looks like it might be technically possible for armv8 (including -a)
> to lack FP in aarch32 state (unlike aarch64 state), but I went looking
> for real existing 32-bit only armv8 chips lacking FP and found only
> stuff like Cortex M23, and they're using armv8-m (embedded profile,
> lots of other stuff missing or optional).  The weakest 32 bit-only
> armv8-a chip I could find in a quick search was the Cortex A32 but it
> looks like it has FP.  I don't know enough about any of this stuff to
> guess what's going on here.

I'm confused too, because the gcc documentation is quite definite
that -march=armv8-a assumes FP support by default.  It seems like
somebody broke that for no very good reason and didn't bother to
update the docs either.  Maybe it's actually a bug?

Mainline Linux distros like Fedora and Debian seem to have dropped
32-bit ARM altogether, but there's still a build available from
https://www.raspberrypi.com/software/operating-systems/
that says it is based on Debian bookworm.  I installed that on
my RPi4 and found that it has

$ gcc -v
Using built-in specs.
COLLECT_GCC=gcc
COLLECT_LTO_WRAPPER=/usr/lib/gcc/arm-linux-gnueabihf/12/lto-wrapper
Target: arm-linux-gnueabihf
Configured with: ... --with-arch=armv6+fp --with-float=hard ...
Thread model: posix
Supported LTO compression algorithms: zlib zstd
gcc version 12.2.0 (Raspbian 12.2.0-14+rpi1) 

So, just like NetBSD's "generic" ARM32 build, they are firmly in
the hard-float camp.  There may be builds out there that will
still work on soft-float ARM, but they've got to be scarce ...
and you'd have to wonder why anybody would be trying to run PG
on such hardware anyway.

Anyway, experimentation shows that this gcc version gives the same
"selected processor lacks an FPU" failure with "-march=armv8-a+crc".
It will not take "-march=armv8-a+crc+fp", but it will take
"-march=armv8-a+crc -mfpu=vfpv3"; the same holds for NetBSD 10.0's
gcc 10.5.0.  Possibly other -mfpu settings will work (I recall having
had success yesterday with -mfpu=neon on NetBSD), but I think this is
a pretty generic setting: per the gcc docs it corresponds to typical
armv7 hardware.

I've checked the attached patch on both the raspberrypi system and
NetBSD 10.0.

            regards, tom lane

diff --git a/configure b/configure
index 28719ed30c..d61a7e59dd 100755
--- a/configure
+++ b/configure
@@ -17578,8 +17578,10 @@ rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext
 # Check for ARMv8 CRC Extension intrinsics to do CRC calculations.
 #
 # First check if __crc32c* intrinsics can be used with the default compiler
-# flags. If not, check if adding -march=armv8-a+crc flag helps.
-# CFLAGS_CRC is set if the extra flag is required.
+# flags. If not, check if adding -march=armv8-a+crc flag helps. On systems
+# using hard-float ABI, it may be that "-march=armv8-a+crc" will be rejected
+# but "-march=armv8-a+crc -mfpu=vfpv3" will work, so next try that.
+# CFLAGS_CRC is set if extra flag(s) are required.
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for __crc32cb, __crc32ch, __crc32cw, and __crc32cd with CFLAGS=" >&5
 $as_echo_n "checking for __crc32cb, __crc32ch, __crc32cw, and __crc32cd with CFLAGS=... " >&6; }
 if ${pgac_cv_armv8_crc32c_intrinsics_+:} false; then :
@@ -17661,6 +17663,48 @@ if test x"$pgac_cv_armv8_crc32c_intrinsics__march_armv8_apcrc" = x"yes"; then
   pgac_armv8_crc32c_intrinsics=yes
 fi

+  if test x"$pgac_armv8_crc32c_intrinsics" != x"yes"; then
+    { $as_echo "$as_me:${as_lineno-$LINENO}: checking for __crc32cb, __crc32ch, __crc32cw, and __crc32cd with
CFLAGS=-march=armv8-a+crc-mfpu=vfpv3" >&5 
+$as_echo_n "checking for __crc32cb, __crc32ch, __crc32cw, and __crc32cd with CFLAGS=-march=armv8-a+crc -mfpu=vfpv3...
">&6; } 
+if ${pgac_cv_armv8_crc32c_intrinsics__march_armv8_apcrc__mfpu_vfpv3+:} false; then :
+  $as_echo_n "(cached) " >&6
+else
+  pgac_save_CFLAGS=$CFLAGS
+CFLAGS="$pgac_save_CFLAGS -march=armv8-a+crc -mfpu=vfpv3"
+cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+/* end confdefs.h.  */
+#include <arm_acle.h>
+int
+main ()
+{
+unsigned int crc = 0;
+   crc = __crc32cb(crc, 0);
+   crc = __crc32ch(crc, 0);
+   crc = __crc32cw(crc, 0);
+   crc = __crc32cd(crc, 0);
+   /* return computed value, to prevent the above being optimized away */
+   return crc == 0;
+  ;
+  return 0;
+}
+_ACEOF
+if ac_fn_c_try_link "$LINENO"; then :
+  pgac_cv_armv8_crc32c_intrinsics__march_armv8_apcrc__mfpu_vfpv3=yes
+else
+  pgac_cv_armv8_crc32c_intrinsics__march_armv8_apcrc__mfpu_vfpv3=no
+fi
+rm -f core conftest.err conftest.$ac_objext \
+    conftest$ac_exeext conftest.$ac_ext
+CFLAGS="$pgac_save_CFLAGS"
+fi
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $pgac_cv_armv8_crc32c_intrinsics__march_armv8_apcrc__mfpu_vfpv3" >&5
+$as_echo "$pgac_cv_armv8_crc32c_intrinsics__march_armv8_apcrc__mfpu_vfpv3" >&6; }
+if test x"$pgac_cv_armv8_crc32c_intrinsics__march_armv8_apcrc__mfpu_vfpv3" = x"yes"; then
+  CFLAGS_CRC="-march=armv8-a+crc -mfpu=vfpv3"
+  pgac_armv8_crc32c_intrinsics=yes
+fi
+
+  fi
 fi

 # Check for LoongArch CRC intrinsics to do CRC calculations.
diff --git a/configure.ac b/configure.ac
index 533f4ab78a..7bed68c7de 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2093,11 +2093,16 @@ AC_COMPILE_IFELSE([AC_LANG_PROGRAM([], [
 # Check for ARMv8 CRC Extension intrinsics to do CRC calculations.
 #
 # First check if __crc32c* intrinsics can be used with the default compiler
-# flags. If not, check if adding -march=armv8-a+crc flag helps.
-# CFLAGS_CRC is set if the extra flag is required.
+# flags. If not, check if adding -march=armv8-a+crc flag helps. On systems
+# using hard-float ABI, it may be that "-march=armv8-a+crc" will be rejected
+# but "-march=armv8-a+crc -mfpu=vfpv3" will work, so next try that.
+# CFLAGS_CRC is set if extra flag(s) are required.
 PGAC_ARMV8_CRC32C_INTRINSICS([])
 if test x"$pgac_armv8_crc32c_intrinsics" != x"yes"; then
   PGAC_ARMV8_CRC32C_INTRINSICS([-march=armv8-a+crc])
+  if test x"$pgac_armv8_crc32c_intrinsics" != x"yes"; then
+    PGAC_ARMV8_CRC32C_INTRINSICS([-march=armv8-a+crc -mfpu=vfpv3])
+  fi
 fi

 # Check for LoongArch CRC intrinsics to do CRC calculations.
diff --git a/meson.build b/meson.build
index b64d253fe4..4bf730e40a 100644
--- a/meson.build
+++ b/meson.build
@@ -2294,6 +2294,13 @@ int main(void)
     cdata.set('USE_ARMV8_CRC32C', false)
     cdata.set('USE_ARMV8_CRC32C_WITH_RUNTIME_CHECK', 1)
     have_optimized_crc = true
+  elif cc.links(prog, name: '__crc32cb, __crc32ch, __crc32cw, and __crc32cd with -march=armv8-a+crc -mfpu=vfpv3',
+      args: test_c_args + ['-march=armv8-a+crc', '-mfpu=vfpv3'])
+    # Use ARM CRC Extension, with runtime check
+    cflags_crc += ['-march=armv8-a+crc', '-mfpu=vfpv3']
+    cdata.set('USE_ARMV8_CRC32C', false)
+    cdata.set('USE_ARMV8_CRC32C_WITH_RUNTIME_CHECK', 1)
+    have_optimized_crc = true
   endif

 elif host_cpu == 'loongarch64'