Re: Reduce timing overhead of EXPLAIN ANALYZE using rdtsc? - Mailing list pgsql-hackers

From John Naylor
Subject Re: Reduce timing overhead of EXPLAIN ANALYZE using rdtsc?
Date
Msg-id CANWCAZbJfyoX-e5gxMBKBb=04FBDz_pTsqb4Poij_AHiu29K9g@mail.gmail.com
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In response to Re: Reduce timing overhead of EXPLAIN ANALYZE using rdtsc?  (Lukas Fittl <lukas@fittl.com>)
Responses Re: Reduce timing overhead of EXPLAIN ANALYZE using rdtsc?
List pgsql-hackers
On Fri, Apr 3, 2026 at 6:16 AM Lukas Fittl <lukas@fittl.com> wrote:
> v16

Just some minor quibbles on 0002:

--- a/src/include/port/pg_cpu.h
+++ b/src/include/port/pg_cpu.h
@@ -23,6 +23,12 @@ typedef enum X86FeatureId
  /* scalar registers and 128-bit XMM registers */
  PG_SSE4_2,
  PG_POPCNT,
+ PG_HYPERVISOR,

The hypervisor flag doesn't really belong with an instruction family.
Maybe a separate category like "identification"?

+ /* TSC flags */
+ PG_RDTSCP,
+ PG_TSC_INVARIANT,
+ PG_TSC_ADJUST,

Maybe spell out time stamp counter in the comment, since this will be
the first time the reader encounters that in this file.

+ * For some other Hypervisors that have an invariant TSC, e.g. HyperV, we would
+ * need to access an MSR to get the frequency (which is typically not available

Maybe spell out MSR too, because I for one don't know what that is.

+ X86Features[PG_HYPERVISOR] = reg[ECX] >> 31 & 1;
+ have_osxsave = reg[ECX] & (1 << 27);
+
+ pg_cpuid_subleaf(0x07, 0, reg);
+
+ X86Features[PG_TSC_ADJUST] = (reg[EBX] & (1 << 1)) != 0;

Some inconsistency in shift style.

--
John Naylor
Amazon Web Services



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