Re: Caching by Postgres - Mailing list pgsql-performance

From mark@mark.mielke.cc
Subject Re: Caching by Postgres
Date
Msg-id 20050825001320.GA18300@mark.mielke.cc
Whole thread Raw
In response to Re: Caching by Postgres  (Alan Stange <stange@rentec.com>)
List pgsql-performance
On Wed, Aug 24, 2005 at 05:09:04PM -0400, Alan Stange wrote:
> The older 32bit RISC processors do have 64 bit registers, ALUs and
> datapaths, and they are marketed toward high end scientific computing,
> and you're claiming that such a processor is slower than one which has
> the addition of 64 bit pointers added to it?

No. I'm claiming that you are talking about a hybrid 64/32 processor,
and that this isn't fair to declare that 64-bit arithmetic units don't
provide benefit for 64-bit math. :-)

> As an example, an UltraSparc running a 32 bit kernel+application will
> have the same double precision floating point performance as one
> running  a 64bit kernel+application (except for the additional FP
> registers in the 64bit API).  For a function like daxpy, it's the exact
> same hardware running the exact same instructions!  So why do you think
> the performance would be different?

Double precision floating point isn't 64-bit integer arithmetic. I think
this is all a little besides the point. If you point is that the SPARC
was designed well - I agree with you.

I won't agree that a SPARC with 64-bit registers should be considered
a 32-bit machine. The AMD 64-bit machines come in two forms as well -
the ones that allow you to use the 64-bit integer registers (not
floating point! those are already 80-bit!), and the ones that allow
you to address more memory. I wouldn't consider either to be a 32-bit
CPU, although they will allow 32-bit applications to run fine.

> I believe the IBM Power processors also upped everything to double
> precision internally because of some details of the "multiply-add fused"
> instructions.  It's been a few years since I taught H&P to CS
> undergrads, but I'm fairly sure the details are all the same for MIPS
> processors as well.

Smart design, that obscures the difference - but doesn't make the
difference a myth. If it's already there, then it's already there,
and we can't talk as if it isn't.

Cheers,
mark

--
mark@mielke.cc / markm@ncf.ca / markm@nortel.com     __________________________
.  .  _  ._  . .   .__    .  . ._. .__ .   . . .__  | Neighbourhood Coder
|\/| |_| |_| |/    |_     |\/|  |  |_  |   |/  |_   |
|  | | | | \ | \   |__ .  |  | .|. |__ |__ | \ |__  | Ottawa, Ontario, Canada

  One ring to rule them all, one ring to find them, one ring to bring them all
                       and in the darkness bind them...

                           http://mark.mielke.cc/


pgsql-performance by date:

Previous
From: "Jim C. Nasby"
Date:
Subject: Re: Read/Write block sizes
Next
From: "Jim C. Nasby"
Date:
Subject: RAID arrays (and vendors)