Re: [COMMITTERS] pgsql: Move each SLRU's lwlocks to a separate tranche. - Mailing list pgsql-hackers
From | Robert Haas |
---|---|
Subject | Re: [COMMITTERS] pgsql: Move each SLRU's lwlocks to a separate tranche. |
Date | |
Msg-id | CA+TgmoZyRUV=SFEppyDiDNApEH_p=5C8_GSnochQRQksVSpAAQ@mail.gmail.com Whole thread Raw |
In response to | Re: [COMMITTERS] pgsql: Move each SLRU's lwlocks to a separate tranche. (Tom Lane <tgl@sss.pgh.pa.us>) |
Responses |
Re: [COMMITTERS] pgsql: Move each SLRU's lwlocks to a separate tranche.
|
List | pgsql-hackers |
On Fri, Mar 25, 2016 at 9:48 AM, Tom Lane <tgl@sss.pgh.pa.us> wrote: > Robert Haas <robertmhaas@gmail.com> writes: >> It's stupid that we keep spending time and energy figuring out which >> shared memory data structures require alignment and which ones don't. >> Let's just align them *all* and be done with it. The memory cost >> shouldn't be more than a few kB. > > I think such a proposal should come with a measurement, not just > speculation about what it costs. About 6kB with default settings. See below. LOG: shared memory size: 148471808 LOG: size 48 -> maxalign 48, cachelinealign 128, delta 80 LOG: size 25988 -> maxalign 25992, cachelinealign 26112, delta 120 LOG: size 2904 -> maxalign 2904, cachelinealign 2944, delta 40 LOG: size 264 -> maxalign 264, cachelinealign 384, delta 120 LOG: size 4209296 -> maxalign 4209296, cachelinealign 4209408, delta 112 LOG: size 529216 -> maxalign 529216, cachelinealign 529280, delta 64 LOG: size 133600 -> maxalign 133600, cachelinealign 133632, delta 32 LOG: size 32 -> maxalign 32, cachelinealign 128, delta 96 LOG: size 267072 -> maxalign 267072, cachelinealign 267136, delta 64 LOG: size 66880 -> maxalign 66880, cachelinealign 66944, delta 64 LOG: size 133600 -> maxalign 133600, cachelinealign 133632, delta 32 LOG: size 948 -> maxalign 952, cachelinealign 1024, delta 72 LOG: size 2904 -> maxalign 2904, cachelinealign 2944, delta 40 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 20640 -> maxalign 20640, cachelinealign 20736, delta 96 LOG: size 28 -> maxalign 32, cachelinealign 128, delta 96 LOG: size 2904 -> maxalign 2904, cachelinealign 2944, delta 40 LOG: size 2904 -> maxalign 2904, cachelinealign 2944, delta 40 LOG: size 4100 -> maxalign 4104, cachelinealign 4224, delta 120 LOG: size 2904 -> maxalign 2904, cachelinealign 2944, delta 40 LOG: size 2904 -> maxalign 2904, cachelinealign 2944, delta 40 LOG: size 88 -> maxalign 88, cachelinealign 128, delta 40 LOG: size 2904 -> maxalign 2904, cachelinealign 2944, delta 40 LOG: size 24 -> maxalign 24, cachelinealign 128, delta 104 LOG: size 16 -> maxalign 16, cachelinealign 128, delta 112 LOG: size 133600 -> maxalign 133600, cachelinealign 133632, delta 32 LOG: size 16 -> maxalign 16, cachelinealign 128, delta 112 LOG: size 96 -> maxalign 96, cachelinealign 128, delta 32 LOG: size 95584 -> maxalign 95584, cachelinealign 95616, delta 32 LOG: size 1392 -> maxalign 1392, cachelinealign 1408, delta 16 LOG: size 1 -> maxalign 8, cachelinealign 128, delta 120 LOG: size 488 -> maxalign 488, cachelinealign 512, delta 24 LOG: size 16 -> maxalign 16, cachelinealign 128, delta 112 LOG: size 3016 -> maxalign 3016, cachelinealign 3072, delta 56 LOG: size 69144 -> maxalign 69144, cachelinealign 69248, delta 104 LOG: size 940 -> maxalign 944, cachelinealign 1024, delta 80 LOG: size 4760 -> maxalign 4760, cachelinealign 4864, delta 104 LOG: size 327720 -> maxalign 327720, cachelinealign 327808, delta 88 LOG: size 224 -> maxalign 224, cachelinealign 256, delta 32 LOG: size 56 -> maxalign 56, cachelinealign 128, delta 72 LOG: size 1192 -> maxalign 1192, cachelinealign 1280, delta 88 LOG: size 1356 -> maxalign 1360, cachelinealign 1408, delta 48 LOG: size 656 -> maxalign 656, cachelinealign 768, delta 112 LOG: size 1832 -> maxalign 1832, cachelinealign 1920, delta 88 LOG: size 66880 -> maxalign 66880, cachelinealign 66944, delta 64 LOG: total additional space consumed due to cache line alignment = 6096 -- Robert Haas EnterpriseDB: http://www.enterprisedb.com The Enterprise PostgreSQL Company
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