Re: Remove Instruction Synchronization Barrier in spin_delay() for ARM64 architecture - Mailing list pgsql-hackers

From Tom Lane
Subject Re: Remove Instruction Synchronization Barrier in spin_delay() for ARM64 architecture
Date
Msg-id 1650263.1746130086@sss.pgh.pa.us
Whole thread Raw
In response to Re: Remove Instruction Synchronization Barrier in spin_delay() for ARM64 architecture  (Nathan Bossart <nathandbossart@gmail.com>)
Responses Re: Remove Instruction Synchronization Barrier in spin_delay() for ARM64 architecture
Re: Remove Instruction Synchronization Barrier in spin_delay() for ARM64 architecture
List pgsql-hackers
Nathan Bossart <nathandbossart@gmail.com> writes:
> ... commit 3d0b4b1 recently added a non-locking
> initial test in AArch64's TAS_SPIN, so I wonder if the ISB is still
> appropriate.  It'd be interesting to see the performance difference of
> removing the ISB with and without commit 3d0b4b1 applied.

Oh!  That's an excellent point.  The OP didn't mention if their tests
were done before or after 3d0b4b1, but that might well matter.

I still think pgbench is a very blunt tool for this type of testing,
though.  I recommend resurrecting the test_shm_mq-based hack discussed
in the prior thread and seeing what that shows.

            regards, tom lane



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